This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No.2002-119752, filed on Apr. 22, 2002, the entire contents of which are incorporated herein by reference.
1) Field of the Invention
The present invention relates to a low power consumption type direct memory access (DMA) controller.
2) Description of the Related Art
A demand for low power consumption electrical equipments is rising. Accordingly, microcomputers used in the electrical equipments are desired to operate with low power consumption. On the other hand, performance of the electrical equipments is increasing day by day. It is, therefore, necessary to decrease the power consumption of the electrical equipments without deteriorating the performance, such as the data transfer performance, thereof.
In the field of computers, there is known a DMA transfer method in which data is directly transmitted and received between memories or between a memory and a peripheral device without using a CPU. This method allows speedy data transfer between the memories or between the memory and the peripheral device.
FIG. 1 is a diagram that shows the circuit configuration of a conventional DMA controller. In this DMA controller, if a transfer source address, a transfer destination address, and number of transfers (hereinafter xe2x80x9ctransfer numberxe2x80x9d) are supplied from a data bus 1 to the conventional DMA controller by CPU write, the conventional DMA controller stores the transfer source address in a transfer source address register (SA) 21 and a transfer source reload register (SAR) 22 of a transfer source address generator 2.
The transfer destination address is stored in a transfer destination address register (DA) 31 and a transfer destination reload register (DAR) 32 of a transfer destination address generator 3. Further, the transfer number is stored in a transfer number register (TN) 41 and a transfer number reload register (TNR) 42 of a transfer number setting section 4. The reload function of the DMA controller is realized by storing the initial values in the respective reload registers in this manner.
If present values and initial values are written to the six registers 21, 22, 31, 32, 41 and 42, respectively and a start signal is received, first data transfer starts. The DMA controller outputs the transfer source address and the transfer destination address. By doing so, data stored in a region, which corresponds to the transfer source address, of the memory or the like of a transfer source is written to a region, which corresponds to the transfer destination address, of the memory or the like of a transfer destination.
If the first data transfer is finished, an arithmetic device 24 adds or subtracts a preset adjustment value 25 to or from the value stored in the transfer source address register 21. The value obtained as a result of this arithmetic operation is stored, as a new transfer source address, in the transfer source address register 21 through a selector 23.
Similar operation is performed with regard to the transfer destination address. Namely, if the first data transfer is finished, an arithmetic device 34 adds or subtracts a preset adjustment value 35 to or from the value stored in the transfer destination address register 31. The value obtained as a result of this arithmetic operation result is stored, as a new transfer destination address, in the transfer destination address register 31 through a selector 33. It is assumed here that the adjustment values 25 and 35 have same values.
With regard to the transfer number, if the first data transfer is finished, an arithmetic device 44 subtracts 1 from the value stored in the transfer number register 41. The value obtained as a result of this arithmetic operation is stored, as a new transfer number, in the transfer number register 41 through a selector 43.
Once new values are stored in the transfer source address register 21, the transfer destination address register 31, and the transfer number register 41, respectively, then the second data transfer starts. The data transfer is repeated until the value stored in the transfer number register 41 reaches a maximum number of transfers to be performed (hereinafter xe2x80x9ctransfer final valuexe2x80x9d) (e.g., 1).
If the value stored in the transfer number register 41 becomes the transfer final value and the data transfer is finished, the initial values stored in the transfer source reload register 22, the transfer destination reload register 32, and the transfer number reload register 42, are written to the transfer source address register 21, the transfer destination address register 31, and the transfer number register 41, respectively. The data transfer is repeated in response to a signal that indicates transfer start, again by performing these operations, and is stopped in response to the generation of a stop signal. If the CPU refers to the present transfer source address, the present transfer destination address or the present transfer number, the value stored in the transfer source address register 21, the transfer destination address register 31, or in the transfer number register 41 is fed to the CPU through the data bus 1.
FIG. 2 shows the update timings of the transfer source address register 21 and the transfer destination address register 31, and the read and write timings of transfer data in the conventional DMA controller. As shown in FIG. 2, conventionally, the value stored in the transfer source address register 21 is updated right after transfer target data is read from the memory or the like that is the source of the transfer.
Meanwhile, there is proposed an address generation circuit for a DMA controller of an image editing apparatus. See, for example, Japanese Patent Application Laid-Open No. S63-89984. In this DMA controller a register that sets variations (offsets) of a transfer source address and of a transfer destination address is provided, these offsets are added or subtracted to and from the respective addresses of a transfer source, and the respective addresses of a transfer destination are thereby obtained.
According to the conventional DMA controller shown in FIG. 1, however, it is necessary to provide the transfer source address register 21 and the transfer source reload register 22 in the transfer source address generator 2, the transfer destination address register 31 and the transfer destination reload register 32 in the transfer destination address generator 3, and the transfer number register 41 and the transfer number reload register 42 in the transfer number generator 4.
As a result, flip-flops equal to two times the number obtained by multiplying the number of channels by the number of bits of the registers are required in the conventional DMA controller. This disadvantageously increases the power consumption and the circuit scale. Although it may be considered to, for example, decrease frequency so as to suppress the power consumption of the flip-flops, this disadvantageously results in the deterioration of the performance of the DMA controller.
The DMA controller disclosed in the Japanese Patent Application Laid-Open No. S63-89984 is intended to accelerate the data transfer and not to decrease the power consumption.
It is an object of this invention to provide a DMA controller that can decrease power consumption, make circuit scale small, and can be easily incorporated into an existing circuit without deteriorating the performance of the DMA controller.
The DMA controller according to one aspect of the present invention, in which an additive value or a subtractive value of a transfer destination address is equal to an additive value or a subtractive value of a transfer source address, includes a transfer source address storing unit that stores a present value of the transfer source address; a transfer source reload storing unit that stores an initial value of the transfer source address; a first difference calculating unit that obtains a difference between the initial value of the transfer source address and an initial value of the transfer destination address; a difference storing unit that stores the difference obtained by the first difference calculating unit; and a second difference calculating unit that calculates a present value of the transfer destination address based on the difference stored in the difference storing unit and the present value of the transfer source address stored in the transfer source address storing unit.
According to the above aspect, the difference holding unit is provided instead of the conventional transfer destination address register, and a transfer destination reload unit is provided in the transfer destination address generator. Therefore, the number of registers that hold the addresses decrease as compared with the conventional case. The number of flip-flops decreases by the number obtained by multiplying the number of channels by the number of bits of registers, accordingly.
The DMA controller according to another aspect of the present invention, in which an additive value or a subtractive value of a transfer destination address is equal to an additive value or a subtractive value of a transfer source address, includes a transfer destination address storing unit that stores a present value of the transfer destination address; a transfer destination reload storing unit that stores an initial value of the transfer destination address; a first difference calculating unit that obtains a difference between the initial value of the transfer destination address and an initial value of the transfer source address; a difference storing unit that stores the difference obtained by the first difference calculating unit; and a second difference calculating unit that calculates a present value of the transfer source address based on the difference stored in the difference storing unit and the present value of the transfer destination address stored in the transfer destination address storing unit.
According to the above aspect, the difference holding unit is provided instead of the conventional transfer source address register, and a transfer source reload register is provided. Therefore, the number of registers that hold addresses decrease when compared with the conventional case. The number of flip-flops decreases by the number obtained by multiplying the number of channels by the number of bits of registers, accordingly.
These and other objects, features and advantages of the present invention are specifically set forth in or will become apparent from the following detailed descriptions of the invention when read in conjunction with the accompanying drawings.